1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a control circuit and method for controlling a data line switching circuit to secure a stable data output and prevent data by an invalid address from being output, when data read from a memory cell is transmitted to a data output buffer through a sensing circuit in a hyper page mode.
The present application for a control circuit and method for data line switching circuit in a semiconductor memory device is based on Korean Application No. 13265/1995 which is incorporated herein by reference for all purposes.
2. Description of the Related Art
With the high speed and multifunction operation of a microprocessor having an operating frequency of more than 100 MHz, semiconductor memory devices are required to have low access times and high bandwidth. In order to meet this demand, a high speed page mode function was developed for memory devices which allows data within the same "page" to be output at a high rate of speed. Nevertheless, there is a limitation in achieving desirable output rates. Accordingly, in order to overcome this limitation, memory devices having a hyper page mode function capable of providing greater bandwidth than the high speed page mode function have been developed.
The hyper page mode function is in described in detail in a data book owned by the SAMSUNG Electronics Co., Ltd under the heading "Extended Data Out DRAM." Hyper page mode is also referred to as EDO (extended data output) mode, however, it is referred to as hyper page mode in the present application. A description of the hyper page mode function as compared with the high speed page mode is as follows. In the following description an exclamation point (!) denotes a logical negation, which is also indicated by a horizontal bar over a signal name in the drawings. In the hyper page mode, even when a column address strobe signal !CAS is disabled, output data is not changed to a high impedance state. Instead, the output data maintains its own state value even after the column address changes. Next, if the column address strobe signal !CAS is enabled, data by a new column address is output after a given time delay. At this time, if an invalid column address is provided to the device, invalid data may be generated prior to valid data. This deteriorates output characteristics of a chip having the hyper page mode function.
FIG. 1 is a block diagram illustrating a memory device including a prior art control circuit and method for controlling a data line switching circuit. The memory device of FIG. 1 includes a separate decoder for selecting a row and a column, an address transmission detector ATD that detects a transition of an address signal and the row decoder designates data to be stored in a memory cell array. The memory device also includes a bit line sense amplifier that senses designated data and amplifies it to thereby output the amplified data. A column selection gate 25 comprises a plurality of MOS transistors which have output signals of the bit line sense amplifier applied at drains thereof. The column decoder designates specific MOS transistors among a plurality of MOS transistors of the column selection gate 25 and gates the designated MOS transistors so that input/output signals I/O and !I/O are selected.
An input/output sense amplifier senses input/output signals IO and !I/O selected in the column selection gate 25 and amplifies them, and a delay circuit receives a column address strobe signal !CAS and time-delays it, thereby controlling a data line switching circuit 10 which switches the signal amplified in the I/O sense amplifier to thereby output the sensed data to a data output buffer. A latch circuit 20 comprises a chain of inverters which latch signals output via the data line switching circuit 10 switched by a signal .phi.CD and the signal amplified in the I/O sense amplifier. In FIG. 1, it should be noted that the signal .phi.CD for controlling the data line switching circuit is generated by the first delay circuit receiving the column address strobe signal !CAS. A data output buffer buffers the signal latched by the latch 20. A data line switching method as shown in FIG. 1 has been applied to a wide 4 megabit DRAM that is a product of a Samsung Electronics Co., LTD.
FIG. 2 illustrates an operation timing diagram of the prior art control circuit for controlling the data line switching circuit in the conventional hyper page mode. The operation characteristic of FIG. 1 is explained through FIG. 2 as follows. As stated previously, in the hyper page mode, though the column address strobe signal !CAS is disabled, i.e., logic "high" state, data output in the former read cycle is not changed to the high impedance state but holds the value thereof. In a period where the column address strobe signal !CAS is disabled, the signal .phi.CD is in a logic "low" state. Accordingly, the data line switching circuit 10 is turned off and data of the former cycle is retained by the latch circuit 20. The output state is thereby maintained. This is a characteristic of the hyper page mode function that results from the data output buffer being continuously enabled even when the column address strobe signal !CAS is disabled.
On the other hand, when the column address signal ADD is transmitted, the address transition detector ATD detects such a state change and generates various kinds of pulses, each having a predetermined time period. The technique of controlling a data output by using an address transition signal !.phi.ATS detected by the address transition detector ATD is disclosed by the Toshiba Corporation in U.S. Pat. No. 4,858,197, incorporated herein by reference. As described therein, the address transition signal !.phi.ATS is a negative pulse having a given time period generated in response to a transition of the external column address. The address transition detector ATS generates !.phi.ATS by combining an auto pulse (not shown), which is delayed relative to the address transition by a given time period, together with a valid column address j, as shown in FIG. 2. In this case, the column address signal applied from outside the chip is input within the chip only where a column address latch signal .phi.YAL is at a logic "low" state, which is determined by the state of the !CAS signal. Therefore, in a period where the .phi.YAL signal is a logic "high" state, the address applied from outside is not input within the chip and also the !.phi.ATS signal generated in response to such an address is not generated because the address provided to the ATS did not change.
In a situation when the !.phi.ATS signal is the logic "high" state, data is changed to the input/output signals I/O and !I/O while passing from the memory cell array through the bit line sense amplifier and is then amplified by the I/O sense amplifier to thereby be transmitted to data lines DO and !DO. Next, if the valid column address j is input, the !.phi.ATS goes to a logic "low" state and then has a negative pulse width of a given period. At the same time, the I/O sense amplifier is disabled by the !.phi.ATS during the same pulse period. At this time, the data line switching circuit 10 is turned off due to the .phi.CD signal being supplied as the logic "low" state and therefore, the data lines DO and !DO and the data output buffer are electrically isolated. Accordingly, it should be noted that the .phi.CD signal must maintain the logic "low" state during a given time period, i.e., 3-5 ns, after the .phi.ATS signal is again changed to the logic "high" state. This is because a time of 3-5 ns is required for the I/O sense amplifier to amplify data and the valid data to propagate to the switching circuit 10. The !.phi.ATS signal is combined with the signal acting as a decoded valid column address j while again being supplied as a logic "high" state, to thereby enable the I/O sense amplifier. That is, the data in the memory cell selected by the column address j is amplified. The signal .phi.CD, which is used as both a signal for controlling the data line switching circuit 10 and a delay signal of the column address strobe signal !CAS, is supplied to the switching circuit 10 at the logic "high" state. Accordingly, data amplified in the I/O sense amplifier is transmitted through the data line switching circuit 10 to the data output buffer, and thereby updated data is output.
If, on the other hand, valid column address j is provided after address transition signal !.phi.ATS again changes from a logic "low" state to a logic "high" state, for example, if a valid address setup time occurs thereafter, data by the invalid column address i is transmitted through the I/O sense amplifier to the data lines DO and !DO when .phi.CD is at a logic "high" state. This causes a problem in that data by the invalid column address i is output to a data output terminal through the data output buffer. This problem is illustrated in FIG. 2 where the invalid data produced by the invalid column address i is output during a period Q. This phenomenon occurs when !.phi.ATS changes from a logic "low" state to a logic "high" state before the signal .phi.CD. Accordingly, in the semiconductor memory device having the prior art control circuit for controlling the data line switching circuit, there is a problem that data by the invalid column address i is output through the data output buffer to the data output terminal.